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february 2014 ? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor FDMF5820DC ? smart power stage (sps) module with integrated temperature monitor features ? ultra-compact 5 mm x 5 mm pqfn copper-clip package with flip chip low-side mosfet and dual cool architecture ? high current handling: 60 a ? 3-state 3.3 v pwm input gate driver ? dynamic resistance mode for low-side drive (ldrv) slows low-side mosfet during negative inductor current switching ? auto dcm (low-side ga te turn off) using zcd# input ? thermal monitor for module temperature reporting ? programmable thermal shutdown (p_thdn) ? hs-short detect fault# / shutdown ? dual mode enable / fault# pin ? internal pull-up and pull-down for zcd# and en inputs, respectively ? fairchild powertrench ? mosfets for clean voltage waveforms and reduced ringing ? fairchild syncfet? technology (integrated schottky diode) in low-side mosfet ? integrated bootstrap schottky diode ? optimized / extremely short dead-times ? under-voltage lockout (uvlo) on vcc ? optimized for switching frequencies up to 1.5 mhz ? pwm minimum controllable on-time: 30 ns ? low shutdown current: < 3 a ? optimized fet pair fo r highest efficiency: 10 ~ 15% duty cycle ? operating ambient te mperature range: -40c to +125c ? fairchild green packaging and rohs compliance description the sps family is fairchild?s next-generat ion, fully optimized, ultra-compact, in tegrated mosfet plus driver power stage solution for high-current, high- frequency, synchronous buck, dc-dc applications. the FDMF5820DC integrates a dr iver ic with a bootstrap schottky diode, two power mosfets, and a thermal monitor into a thermally enhanced, ultra-compact, 5 mm x 5 mm package. with an integrated approach, the sps switching power stage is optimized for driver and mosfet dynamic performance, minimized system inductance, and power mosfet r ds(on) . the sps family uses fairchild's high- performance powertrench ? mosfet technology, which reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. a driver ic with reduced dead times and propagation delays further enhances the performance. a thermal monitor function warns of a potential over-temperature situation. a programmable t hermal shutdown function turns off the driver if an over-temperature condition occurs. the FDMF5820DC incorporates an auto-dcm mode (zcd#) for improved light-load efficiency. the FDMF5820DC also provides a 3-state 3.3 v pwm input for compatibility with a wide range of pwm controllers. applications ? servers and workstations, v-core and non-v-core dc-dc converters ? desktop and all-in-one computers, v-core and non-v-core dc-dc converters ? high-performance gaming motherboards ? high-current dc-dc point-of-load converters ? networking and telecom microprocessor voltage regulators ? small form-factor voltage regulator modules ordering information part number current rating package top mark FDMF5820DC 60 a 31-lead, clip bond pqfn sps, 5.0 mm x 5.0 mm package FDMF5820DC
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 2 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor application diagram figure 1. typical application diagram functional block diagram figure 2. functional block diagram
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 3 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor pin configuration figure 3. pin configuration - top view and transparent view pin definitions pin # name description 1 pwm pwm input to the gate driver ic 2 zcd# enable input for the zcd (auto dcm) comparator 3 vcc power supply input for all analog co ntrol functions; this is the ?quiet? v cc 4, 32 agnd analog ground for analog port ions of the ic and for substrate 5 boot supply for the high-side mosfet gate driver . a capacitor from boot to phase supplies the charge to turn on the n-channel high-side mosfet 6 nc no connect 7 phase return connection for the boot capacitor, internally tied to sw node 8~11 vin power input for the power stage 12~15, 28 pgnd power return for the power stage 16~26 sw switching node junction between high-side and low-side mosfets; also input to the gate driver sw node comparator and input into the zcd comparator 27, 33 gl gate low, low-side mosfet gate monitor 29 pvcc power supply input for ls (1) gate driver and boot diode 30 tmon temperature monitoring & reporti ng / programmable thermal shutdown pin 31 en / fault# dual-functionality: enable input to the gate driver ic; fault# - internal pull-down physically pulls this pin low upon detection of fault condition (hs (2) mosfet short or tmon signal exceeding 1.5 v) notes: 1. ls = low side. 2. hs = high side.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 4 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. t a = t j = 25c symbol parameter min. max. unit v cc supply voltage referenced to agnd -0.3 6.0 v pv cc drive voltage referenced to agnd -0.3 6.0 v v en/fault# output enable / disable referenced to agnd -0.3 6.0 v v pwm pwm signal input referenced to agnd -0.3 6.0 v v zcd# zcd mode input referenced to agnd -0.3 6.0 v v gl low gate manufacturing test pin referenced to agnd -0.3 6.0 v v tmon thermal monitor referenced to agnd -0.3 6.0 v v in power input referenced to pgnd, agnd -0.3 25.0 v v phase phase referenced to pgnd, agnd (dc only) -0.3 25.0 v referenced to pgnd, ac < 20 ns -5.0 30.0 v sw switch node input referenced to pgnd, agnd (dc only) -0.3 25.0 v referenced to pgnd, ac < 20 ns -5.0 30.0 v boot bootstrap supply referenced to agnd (dc only) -0.3 30.0 v referenced to agnd, ac < 20 ns -5.0 35.0 v boot-phase boot to phase voltage referenced to pvcc -0.3 6.0 v i o(av) (3) output current f sw = 300 khz, v in =12 v, v out =1.8 v 60 a f sw = 1 mhz, v in =12 v, v out =1.8 v 55 i fault en / fault# sink current -0.1 7.0 ma j-a junction-to-ambient thermal resistance 12.4 c/w j-pcb junction-to-pcb thermal re sistance (under fairchild sps thermal board) 1.8 c/w t a ambient temperature range -40 +125 c t j maximum junction temperature +150 c t stg storage temperature range -55 +150 c esd electrostatic discharge protection human body model, ansi/esda/jedec js-001-2012 3000 v charged device model, jesd22-c101 2500 note: 3. i o(av) is rated with testing fairch ild?s sps evaluatio n board at t a = 25c with natural convection cooling. this rating is limited by the peak sps temperature, t j = 150c, and varies depending on operating conditions and pcb layout. this rating may be changed with different application settings . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v cc control circuit supply voltage 4.5 5.0 5.5 v pv cc gate drive circuit supply voltage 4.5 5.0 5.5 v v in output stage supply voltage 4.5 (4) 12.0 16.0 (5) v notes: 4. 3.0 v v in is possible according to the application condition. 5. operating at high v in can create excessive ac voltage overs hoots on the sw-to-gnd and boot-to-gnd nodes during mosfet switching transient. for reliable sps operat ion, sw to gnd and boot to gnd must remain at or below the absolute maximum ratings in the table above.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 5 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor electrical characteristics typical value is under v in =12 v, v cc =pv cc =5 v and t a =t j =+ 25c unless otherwise noted. minimum / maximum values are under v in =12 v, v cc =pv cc =5 v 10% and t j =t a =-40 ~ 125c unless otherwise noted. symbol parameter condition min. typ. max. unit basic operation i q quiescent current i q =i vcc + i pvcc , en=high, pwm=low or high or float (non-switching) 2 ma i shdn shutdown current i shdn =i vcc + i pvcc , en=gnd 3 a v uvlo uvlo threshold v cc rising 3.5 3.8 4.1 v v uvlo_hyst uvlo hysteresis 0.4 v t d_por por delay to enable ic v cc uvlo rising to internal pwm enable 20 s en input v ih_en high-level input voltage 2.0 v v il_en low-level input voltage 0.8 v r pld_en pull-down resistance 250 k ? t pd_enl en low propagation delay pwm=gnd, en going low to gl going low 25 ns t pd_enh en high propagation delay pwm=gnd, en going high to gl going high 20 s zcd# input v ih_zcd# high-level input voltage 2.0 v v il_zcd# low-level input voltage 0.8 v i plu_zcd# pull-up current 10 a t pd_zlgll zcd# low propagation delay pwm=gnd, zcd# going low to gl going low (assume i l <=0) 10 ns t pd_zhglh zcd# high propagation delay pwm=gnd, zcd# going high to gl going high 10 ns pwm input r up_pwm pull-up impedance typical values: t a =t j =25c, v cc =pv cc =5 v, min. / max. values: t a =t j =-40c to 125c, v cc =pv cc =5 v 10% 23 k ? r dn_pwm pull-down impedance 10 k ? v ih_pwm pwm high level voltage 2.2 v v tri_window 3-state window 1.2 1.8 v v il_pwm pwm low level voltage 0.8 v t d_hold-off 3-state shut-off time 90 130 ns v hiz_pwm 3-state open volt age 1.3 1.5 1.7 v minimum contro llable on-time t min_pwm_on pwm minimum controllable on- time minimum pwm high pulse required for sw node to switch from gnd to vin 30 ns forced minimum gl high time t min_gl_high forced minimum gl high minimum gl high time when low v boot-sw detected and pwm low=<100 ns 100 ns pwm propagation delays & dead times (v in =12 v, v cc =pv cc =5 v, f sw =1 mhz, i out =20 a, t a =25 c ) t pd_phgll pwm high propagation delay pwm going high to gl going low, v ih_pwm to 90% gl 15 ns t pd_plghl pwm low propagation delay pwm going low to gh (6) going low, v il_pwm to 90% gh 30 ns t pd_phghh pwm high propagation delay (zcd# held low) pwm going high to gh going high, v ih_pwm to 10% gh (zcd#=low, i l =0, assumes dcm) 10 ns continued on the following page?
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 6 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor electrical characteristics typical value is under v in =12 v, v cc =pv cc =5 v and t a =t j =+ 25c unless otherwise noted. minimum / maximum values are under v in =12 v, v cc =pv cc =5 v 10% and t j =t a =-40 ~ 125c unless otherwise noted. symbol parameter condition min. typ. max. unit t d_deadon ls off to hs on dead time gl going low to gh going high, 10% gl to 10% gh, pwm transition low to high ? see figure 27 10 ns t d_deadoff hs off to ls on dead time gh going low to gl going high, 10% gh to 10% gl, pwm transition high to low ? see figure 27 5 ns t r_gh_20a gh rise time under 20 a i out 10% gh to 90% gh, i out =20 a 9 ns t f_gh_20a gh fall time under 20 a i out 90% gh to 10% gh, i out =20 a 9 ns t r_gl_20a gl rise time under 20 a i out 10% gl to 90% gl, i out =20 a 9 ns t f_gl_20a gl fall time under 20 a i out 90% gl to 10% gl, i out =20 a 6 ns t pd_tsghh exiting 3-state propagation delay pwm (from 3-state) going high to gh going high, v ih_pwm to 10% gh 45 ns t pd_tsglh exiting 3-state propagation delay pwm (from 3-state) going low to gl going high, v il_pwm to 10% gl 45 ns high-side driver (hdrv, v cc = pv cc = 5 v) r source_gh output impedance, sourcing source current=100 ma 0.68 ? r sink_gh output impedance, sinking sink current=100 ma 0.9 ? t r_gh gh rise time 10% gh to 90% gh, c load =1.3 nf 4 ns t f_gh gh fall time 90% gh to 10% gh, c load =1.3 nf 3 ns weak low-side driver (ldrv2 on ly under ccm2 mode operation, v cc = pv cc = 5 v) r source_gl output impedance, sourcing source current=100 ma 0.82 ? i source_gl output sourcing peak current gl=2.5 v 2 a r sink_gl output impedance, sinking sink current=100 ma 0.86 ? i sink_gl output sinking peak current gl=2.5 v 2 a low-side driver (paralleled ldrv1 + ldrv2 under ccm1 mode operation, v cc = pv cc = 5 v) r source_gl output impedance, sourcing source current=100 ma 0.47 ? i source_gl output sourcing peak current gl=2.5 v 4 a r sink_gl output impedance, sinking sink current=100 ma 0.29 ? i sink_gl output sinking peak current gl=2.5 v 7 a t r_gl gl rise time 10% gl to 90% gl, c load =7.0 nf 9 ns t f_gl gl fall time 90% gl to 10% gl, c load =7.0 nf 6 ns thermal monitor current i tmon_25 thermal monitor current t a =t j =25c 39.3 40.2 41.0 a i tmon_150 thermal monitor current t a =t j =150c 58 a i tmon_slope thermal monitor current slope t a =t j =25 ~ 150c 0.144 a/c programmable thermal shutdown v act_pthdn activation voltage t a =t j =125 ~ 150c, r tmon =25 k ? 1.39 1.62 v r pld_en-pthdn pull-down resistance t a =t j =25c , i pld_en-pthdn =5 ma 30 ? catastrophic fault (sw monitor) v sw_mon sw monitor reference voltage 1.3 2 v t d_fault propagation delay to pull en / fault# signal = low 20 ns boot diode v f forward-voltage drop i f =10 ma 0.4 v v r breakdown voltage i r =1 ma 30 v note: 6. gh = gate high, internal gate pin of the high-side mosfet.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 7 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor typical performance characteristics test conditions: v in =12 v, v cc =pv cc =5 v, v out =1.8 v, l out =250 nh, t a =25c and natural convection cooling, unless otherwise noted. figure 4. safe operating area figure 5. power loss vs. output current figure 6. power loss vs. switching frequency figure 7. power loss vs. input voltage figure 8. power loss vs. driver supply voltage figure 9. power loss vs. output voltage 0 5 10 15 20 25 30 35 40 45 50 55 60 65 0 25 50 75 100 125 150 module output current, i out [a] pcb temperature, t pcb [c] f sw = 300khz f sw = 1000khz v in = 12v, pv cc & v cc = 5v, v out = 1.8v 0 1 2 3 4 5 6 7 8 9 10 11 12 0 5 10 15 20 25 30 35 40 45 50 55 60 module power loss, pl mod [w] module output current, i out [a] 12vin, 300khz 12vin, 500khz 12vin, 800khz 12vin, 1000khz pv cc & v cc = 5v, v out = 1.8v 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 200 300 400 500 600 700 800 900 1000 1100 normalized module power loss module switching frequency, f sw [khz] v in = 12v, pv cc & v cc = 5v, v out = 1.8v, i out = 30a 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 4 6 8 10 12 14 16 18 normalized module power loss module input voltage, v in [v] pv cc & v vcc = 5v, v out = 1.8v, f sw = 500khz, i out = 30a 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 4.0 4.5 5.0 5.5 6.0 normalized module power loss driver supply voltage, pv cc & v cc [v] v in = 12v, v out = 1.8v, f sw = 500khz, i out = 30a 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 normalized module power loss module output voltage, v out [v] v in = 12v, pv cc & v vcc = 5v, f sw = 500khz, i out = 30a
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 8 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor typical performance characteristics test conditions: v in =12 v, v cc =pv cc =5 v, v out =1.8 v, l out =250 nh, t a =25c and natural convection cooling, unless otherwise noted. figure 10. power loss vs. output inductor figure 11. driver supply current vs. switching frequency figure 12. driver supply current vs. driver supply voltage figure 13. driver supply current vs. output current figure 14. uvlo threshold vs. te mperature figure 15. pwm thres hold vs. driver supply voltage 0.97 0.98 0.99 1.00 1.01 200 250 300 350 400 450 500 normalized module power loss output inductor, l out [nh] v in = 12v, pv cc & v vcc = 5v, f sw = 500khz, v out = 1.8v, i out = 30a 0.01 0.02 0.03 0.04 0.05 0.06 0.07 200 300 400 500 600 700 800 900 1000 1100 driver supply current, i pvcc + i vcc [a] module switching frequency, f sw [khz] v in = 12v, pv cc & v cc = 5v, v out = 1.8v, i out = 0a 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 0.036 4.0 4.5 5.0 5.5 6.0 driver supply current, i pvcc + i vcc [a] driver supply voltage, pv cc & v vcc [v] v in = 12v, v out = 1.8v, f sw = 500khz, i out = 0a 0.88 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 0 5 10 15 20 25 30 35 40 45 50 55 60 normalized driver supply current module output current, i out [a] f sw = 300khz f sw = 1000khz v in = 12v, pv cc & v vcc = 5v, v out = 1.8v 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 -55 0 25 55 100 125 driver supply voltage, v cc [v] driver ic junction temperature, t j [ o c] uvlo up uvlo dn 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 4.50 4.75 5.00 5.25 5.50 pwm threshold voltage, v pwm [v] driver supply voltage, v cc [v] v ih_pwm t a = 25 c v tri_hi v tri_lo v il_pwm v hiz_pwm
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 9 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor typical performance characteristics test conditions: v in =12 v, v cc =pv cc =5 v, v out =1.8 v, l out =250 nh, t a =25c and natural convection cooling, unless otherwise noted. figure 16. pwm threshold vs. temperature fi gure 17. zcd# threshold vs. driver supply voltage figure 18. zcd# threshold vs. temperature figure 19. zcd# pull-up current vs. temperature figure 20. en threshold vs. driv er supply voltage figure 21. en threshold vs. temperature 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 -55 0 25 55 100 125 pwm threshold voltage, v pwm [v] driver ic junction temperature, t j [ o c] v cc = 5v v ih_pwm v tri_hi v hiz_pwm v tri_lo v il_pwm 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 4.50 4.75 5.00 5.25 5.50 zcd# threshold voltage, v zcd# [v] driver supply voltage, v cc [v] v ih_zcd# v il_zcd# t a = 25 c 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -55 0 25 55 100 125 zcd# threshold voltage, v zcd# [v] driver ic junction temperature, t j [ o c] v ih_zcd# v il_zcd# v cc = 5v 0.1 0.12 0.14 0.16 0.18 0.2 0.22 -55 0 25 55 100 125 zcd# pull-up current, i plu [ua] driver ic junction temperature, t j [ o c] v cc = 5v 1.0 1.2 1.4 1.6 1.8 2.0 2.2 4.50 4.75 5.00 5.25 5.50 en threshold voltage, v en [v] driver supply voltage, v cc [v] v ih_en v il_en t a = 25 c 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -55 0 25 55 100 125 en threshold voltage, v en [v] driver ic junction temperature, t j [ o c] v ih_en v il_en v cc = 5v
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 10 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor typical performance characteristics test conditions: v in =12 v, v cc =pv cc =5 v, v out =1.8 v, l out =250 nh, t a =25c and natural convection cooling, unless otherwise noted. figure 22. en pull-down current vs. temperature figure 23. boot diode forward voltage vs. temperature figure 24. driver shutdown current vs. temperature figure 25. driver quiescent current vs. temperature 0.37 0.38 0.39 0.4 0.41 0.42 0.43 -55 0 25 55 100 125 en pull-down current, i pld [ua] driver ic junction temperature, t j [ o c] v cc = 5v 300 350 400 450 500 -55 0 25 55 100 125 boot diode forward voltage, v f [mv] driver ic junction temperature, t j [ o c] i f = 10ma -1 -0.5 0 0.5 1 1.5 2 2.5 -55 0 25 55 100 125 driver shut-down current, i shdn [ua] driver ic junction temperature, t j [ o c] pv cc & v cc = 5v, pwm = 0v, zcd# = 0v, en = 0v 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 -55 0 25 55 100 125 driver quiescent current, i q [ma] driver ic junction temperature, t j [ o c] pv cc & v cc = 5v, zcd# = 5v, en = 5v pwm = 0v pwm = 5v pwm = float
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 11 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor functional description the sps FDMF5820DC is a driver-plus-mosfet module optimized for the sy nchronous buck converter topology. a pwm input signal is required to properly drive the high-side and the low-side mosfets. the part is capable of driving speed up to 1.5 mhz. power-on reset (por) the pwm input stage should in corporate a por feature to ensure both ldrv and hdrv are forced inactive (ldrv = hdrv = 0) until uvlo > ~ 3.8 v (rising threshold). after all gate dr ive blocks are fully powered on and have finished the startup sequence, the internal driver ic en_pwm signal is released high, enabling the driver outputs. once t he driver por has finished (<20 s maximum), the driver follows the state of the pwm signal (it is assumed that at startup the controller is either in a high-impedanc e state or forcing the pwm signal to be within the driver 3-state window). three conditions below must be supported for normal startup / power-up. ? v cc rises to 5 v, then en goes high; ? en pin is tied to the vcc pin; ? en is commanded high prior to 5 v v cc reaching the uvlo rising threshold. the por method is to increase the v cc over than uvlo > rising threshold and en = high. under-voltage lockout (uvlo) uvlo is performed on v cc only, not on pv cc or v in . when the en is set high and v cc is rising over the uvlo threshold level (3.8 v), the part starts switching operation after a maximum 20 s por delay. the delay is implemented to ensure the internal circuitry is biased, stable, and ready to oper ate. two vcc pins are provided: pvcc and vcc. the gate driver circuitry is powered from the pvcc rail. the user connects pvcc to vcc through a low-pass r-c filter. this provides a filtered 5 v bias to the analog circuitry on the ic. figure 26. uvlo on vcc en / fault# (enable / fault flag) the driver can be disabled by pulling the en / fault# pin low (en < v il_en ), which holds both gl and gh low regardless of the pwm i nput state. the driver can be enabled by raising the en / fault# pin voltage high (en > v ih_en ). the driver ic has less than 3 a shutdown current when it is disabled. once the driver is re-enabled, it takes a maximum of 20 s startup time. en / fault# pin is an open-drain output for fault flag with an internal 250 k ? pull-down resistor. logic high signal from pwm controller or a ~ 10 k ? external pull-up resistor from en / fault# pin to vcc is required to start driver operation. table 1. uvlo and enable logic uvlo en driver state 0 x disabled (gh & gl = 0) 1 0 disabled (gh & gl = 0) 1 1 enabled ( see table 2 ) 1 open disabled (gh & gl = 0) the en / fault# pin has two functions: enabling / disabling driver and fault flag. the fault flag signal is active low. when the driver detects a fault condition during operation, it turns on the open-drain on the en / fault# pin and the pin voltage is pulled low. the fault conditions are: ? high-side mosfet false turn-on or vin ~ sw short during low-side mosfet turn on; ? p-thdn by exceeding 1.5 v on tmon pin. when the driver detects a f ault condition and disables itself, a por event on vcc is required to restart the driver operation. 3-state pwm input the FDMF5820DC incorporates a 3-state 3.3 v pwm input gate drive design. the 3-state gate drive has both logic high and low levels, along with a 3-state shutdown window. when the pwm input signal enters and remains within the 3-state window for a defined hold-off time (t d_hold-off ), both gl and gh are pulled low. this feature enables th e gate drive to shut down both the high-side and the low-side mosfets to support features such as phase shedding, a common feature on multi-phase voltage regulators. table 2. en / pwm / 3-state / zcd# logic states en pwm zcd# gh gl 0 x x 0 0 1 3-state x 0 0 1 0 0 0 1 (il > 0), 0 (il < 0) 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 12 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor pwm gl gh-phase (internal) boot-gnd v ih_pwm v il_pwm 90% 10% t fall_gh t rise_gl sw t pd_phgll t pd_plghl t d_deadoff t d_deadon t fall_gl t rise_gh 90% 10% 90% 10% 90% 10% t pd_phgll = pwm hi to gl lo, v ih_pwm to 90% gl t fall_gl = 90% gl to 10% gl t d_deadon = ls off to hs on dead time, 10% gl to v boot-gnd <= pv cc -v f_dboot - 1v or boot-gnd dip start point t rise_gh = 10% gh to 90% gh, v boot-gnd <= pv cc -v f_dboot - 1v or boot-gnd dip start point to gl bounce start point t pd_plghl = pwm lo to gh lo, v il_pwm to 90% gh or boot-gnd decrease start point, t pd_plglh -t d_deadoff -t fall_gh t fall_gh = 90% gh to 10% gh, boot-gnd decrease start point to 90% v sw or gl dip start point t d_deadoff = hs off to ls on dead time, 90% v sw or gl dip start point to 10% gl t rise_gl = 10% gl to 90% gl t pd_plglh = pwm lo to gl hi, v il_pwm to 10% gl t pd_plglh pv cc -v f_dboot -1v 90% figure 27. pwm timing diagram figure 28. pwm threshold definition notes: 7. the timing diagram in figure 28 assumes very slow ramp on pwm. 8. slow ramp of pwm implies the pwm signal rema ins within the 3-state window for a time >>> t d_hold-off. 9. v tri_hi = pwm trip level to enter 3-state on pwm falling edge. 10. v tri_lo = pwm trip level to enter 3-state on pwm rising edge. 11. v ih_pwm = pwm trip level to exit 3-state on pwm ri sing edge and enter the pwm high logic state. 12. v il_pwm = pwm trip level to exit 3-state on pwm fa lling edge and enter the pwm low logic state.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 13 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor power sequence sps FDMF5820DC requires four (4) input signals to conduct normal switching operation: v in , v cc / pv cc , pwm, and en. all combinations of their power sequences are available. the below example of a power sequence is for a reference application design: ? from no input signals -> v in on: typical 12 v dc -> v cc / pv cc on: typical 5 v dc -> en high: typical 5 v dc -> pwm signaling: 3.3 v high / 0 v low the vin pins are tied to the system main dc power rail. pvcc and vcc pins are tied together to supply gate driving and logic circuit powers from the system v cc rail. or the pvcc pin can be directly tied to the system v cc rail, and the vcc pin is powered by pvcc pin through a filter resistor located between pvcc pin and vcc pin. the filter resist or reduces switching noise impact from pv cc to v cc . the en pin can be tied to the v cc rail with an external pull-up resistor and it will maintain high once the v cc rail turns on. or the en pin can be directly tied to the pwm controller for other purposes. high-side driver the high-side driver (hdrv) is designed to drive a floating n-channel mosfet (q1). the bias voltage for the high-side driver is dev eloped by a bootstrap supply circuit, consisting of the internal schottky diode and external bootstrap capacitor (c boot ). during startup, the sw node is held at pgnd, allowing c boot to charge to pvcc through the internal bootstrap diode. when the pwm input goes high, hdrv begins to charge the gate of the high-side mosfet (internal gh pin). during this transition, the char ge is removed from the c boot and delivered to the gate of q1. as q1 turns on, sw rises to v in , forcing the boot pin to v in + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling hdrv to sw. c boot is then recharged to pvcc when the sw falls to pgnd. hdrv output is in phase with the pwm input. the high-side gate is held low when the driver is disabled or the pwm signal is held within the 3-state window for long er than the 3-state hold-off time, t d_hold-off . low-side driver the low-side driver (ldrv) is designed to drive the gate-source of a ground-referenced low r ds(on) , n-channel mosfet (q2). the bias for ldrv is internally connected between the pvcc and agnd. when the driver is enabled, th e driver output is 180 out of phase with the pwm input. when the driver is disabled (en = 0 v), ldrv is held low. continuous current mode 2 (ccm2) operation a main feature of the low-side driver design in sps fmdf5820dc is the ability to control the part of the low-side gate driver upon detection of negative inductor current, called ccm2 operation. this is accomplished by using the zcd comparator signal. the primary reason for scaling back on the drive strength is to limit the peak v ds stress when the low- side mosfet hard-switches inductor current. this peak v ds stress has been an issue with applications with large amounts of load transient and fast and wide output voltage regulation. the mosfet gate driver in sps FDMF5820DC operates in one of three modes, described below. continuous current mode 1 (ccm1) with positive inductor current in this mode, inductor current is always flowing towards the output capacitor, typica l of a heavily loaded power stage. the high-side mosfet turns on with the low- side body diode conducting inductor current and sw is approximately a v f below ground, meaning hard- switched turn-on and turn-off of the high-side mosfet. discontinuous current mode (dcm) typical of lightly loaded power stage; the high-side mosfet turns on with zero inductor current, ramps the inductor current, then returns to zero every switching cycle. when the high-side mosfet turns on under dcm operation, the sw node may be at any voltage from a v f below ground to a v f above v in . this is because after the low-side mosfet turns off, the sw node capacitance resonates with the inductor current. the level shifter in driver ic should be able to turn on the high-side mosfet regardless of the sw node voltage. in this case, the high-side mosfet turns off a positive current. during this mode, both ldrv1 and ldrv2 operate in parallel and the low-side gate driver pull-up and pull- down resistors are oper ating at full strength. continuous current mode 2 (ccm2) with negative inductor current this mode is typical in a synchronous buck converter pulling energy from the output capacitors and delivering the energy to the input capacitors (boost mode). in this mode, the inductor current is negative (meaning towards the mosfets) when the low-side mosfet is turned off (may be negative when the high-side mosfet turns on as well). this situation causes the low-side mosfet to hard switch while the high-side mosfet acts as a synchro nous rectifier (temporarily operated in synchronous boost mode). during this mode, only the ?weak? ldrv2 is used for low-side mosfet turn-on and turn-off. the intention is to slow down the low-side mosfet switching speed when it is hard switching to reduce peak v ds stress. dead-times in ccm1 / dcm / ccm2 the driver ic design ensures minimum mosfet dead times, while eliminating potential shoot-through (cross- conduction) currents. to ensure optimal module efficiency, body diode conduction times must be reduced to the low nano-second range during ccm1 and dcm operation. ccm2 alters the gate drive impedance while operating the power mosfets in a different mode versus ccm1 / dcm. altered dead-time operation must be considered.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 14 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor low-side mosfet off to high-side mosfet on dead time in ccm1 / dcm to prevent overlap during th e low-side mosfet off to high-side mosfet on swit ching transition, adaptive circuitry monitors the voltage at the gl pin. when the pwm signal goes high, gl goes low after a propagation delay (t pd_phgll ). once the gl pin is discharged below ~ 1 ? 2 v, gh is pulled high after an adaptive delay, t d_deadon . some situations where the zcd# rising-edge signal leads the pwm rising edge by tens of nanoseconds, can cause gh and gl overlap. this event can occur when the pwm controller sends pwm and zcd# signals that lead, lag, or are synchronized. to avoid this phenomenon, a secondary fixed propagation delay (t fd_on1 ) is added to ensure there is always a minimum delay between low-side mosfet off to high-side mosfet on. low-side mosfet off to high-side mosfet on dead time in ccm2 as noted in the ccm2 operati on section, the low-side driver strength is scale-able upon detection of ccm2. ccm2 feature slows the charge and discharge of the low-side mosfet gate to minimize peak switching voltage overshoots during low-side mosfet hard- switching (negative inductor current). to avoid cross- conduction, the slowing of the low-side gate also requires an adjustment (i ncrease) of the dead time between low-side mosfet off to high-side mosfet on. a fairly long fixed dead time (t fd_on2 ) is implemented to ensure there is no cross conduction during this ccm2 operation. high-side mosfet off to low-side mosfet on dead time in ccm1 / dcm to get very short dead time during high-side mosfet off to low-side mosfet on transition, a fixed-dead-time method is implemented in the sps gate driver. the fixed-dead-time circuitry monitors the internal hs signal and adds a fixed delay long enough to gate on gl after a desired t d_deadoff (~ 5 ns, t d_deadoff = t fd_off1 ), regardless of sw node state. exiting 3-state condition when exiting a valid 3-state cond ition, the gate driver of the FDMF5820DC follows the pwm input command. if the pwm input goes from 3-st ate to low, the low-side mosfet is turned on. if the pwm input goes from 3- state to high, the high-side mosfet is turned on. this is illustrated in figure 29 below. figure 29. pwm high / low / 3-state timing diagram
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 15 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor exiting 3-state with low boot-sw voltage the sps module is used in multi-phase vr topologies requiring the module to wait in 3-state condition for an indefinite time. these long idle times can bleed the boot capacitor down until eventual clamping occurs based on pv cc and v out . low boot-sw can cause increased propagation delays in the level-shift circuit as well as all hdrv floating circuitry, which is biased from the boot-sw rail. another issue with a depleted boot-sw capacitor voltage is the voltage applied to the hs mosfet gate during turn-on. a low boot-sw voltage results in a very weak hs gate drive, hence, much larger hs r ds(on) and increased risk for unreliable operation since the hs mosfet may not turn-on if boot-sw falls too low. to address this issue, the sps monitors for a low boot-sw voltage when the module is in 3-state condition. when the module exits 3-state condition with a low boot-sw voltage, a 100 ns minimum gl on time is output regardless of the pwm input. this ensures the boot capacitor is adequately charged to a safe operating level and has minimal impact on transient response of the system. scenarios of exiting 3-state condition are listed below. ? if the part exits 3-state with a low boot-sw voltage condition and the controller commands pwm=high, the sps outputs a 100 ns gl pulse and follows the pwm=high command ( see figure 30). ? if the part exits 3-state with a low boot-sw voltage condition and the controller commands pwm=low for 100 ns or more, the sps follows the pwm input. if pwm=low for less than 100 ns, gl remains on for 100 ns then follows the pwm input ( see figure 31 and figure 32) . ? if no low boot-sw condition is detected, the sps follows the pwm command when exiting 3-state ( see figure 33 ). the sps momentarily stays in an adaptive dead time mode when exiting 3-state condi tion or at initial power- up. this adaptive dead time mode lasts for no more than two (2) consecutive switching cycles, giving the boot capacitor ample time to recharge to a safe level. the module switches back to fixed dead time control for maximum efficiency. figure 30. low boot-sw voltage detected and pwm from 3-state to high figure 31. low boot-sw voltage detected and pwm from 3-state to low for more than 100 ns figure 32. low boot-sw voltage detected and pwm from 3-state to low for less than 100 ns figure 33. low boot-sw voltage not detected and pwm from 3-state to high or low
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 16 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor zero cross detect (zcd) operation the zcd control block houses the circuitry that determines when the inductor current reverses direction and controls when to turn off the low-side mosfet. a low offset comparator m onitors the sw-to-pgnd voltage of the low-side mosfet during the ls mosfet on-time. when the sensed voltage switches polarity from negative to pos itive, the comparator changes state and reverse cu rrent has been detected. this comparator offset must sense the negative v sw within a 0.5 mv worst-case range. the negative offset is to ensure the inductor current never reverses; some small body-diode conduction is preferable to having negative current. the comparator is switched on after the rising edge of the low-side gate drive and turned off by the signal at the input to the low-side gate driver. in this way, the zero-current comparator is connected with a break- before-make connection, allowing the comparator to be designed with low-voltage transistors. figure 34. zcd# & pwm timing diagram temperature monitor (tmon) the FDMF5820DC provides a temperature monitor (tmon) to warn of over-temperature conditions. the gate driver uses the tmon pin to source an analog current proportional to absolute temperature (ptat). it is expected that the analog current will be used with a properly chosen external re sistor to agnd to develop a voltage across tmon (v tmon ) proportional to the temperature. a filter capacitance may be needed to minimize noise spikes in the analog current, i tmon . noise spikes are generated from power mosfet switching dv / dt and di / dt coupling back into the driver vcc pin. the tmon pin needs a pull-down resistor (r tmon ) and filter capacitor (c tmon ) to agnd. with 25 k ? r tmon and 0.1 f c tmon , the tmon voltage is around 1 v at 25c of gate driver t j , and 1.5 v when the driver temperature reaches 150c. the v tmon signal can be connected to pwm controller or mcu in system to indicate the thermal status of the gate driver. figure 35 shows gate driver temperature versus tmon pin voltage with 25 k ? r tmon and 0.1 f c tmon . figure 35. gate driver t j vs. v tmon the tmon voltage is defined by following equation: v mv i a r k 18 a 125 drivert 36.4 a r k (1)
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 17 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor programmable thermal shutdown (p-thdn) when the tmon pin voltage ex ceeds 1.5 v, the internal comparator shuts down the driver (en pin goes low). the programmable thermal shutdown temperature range can be adjusted by r tmon so that the shutdown temperature can be custom ized. the equation below shows the relationship between r tmon value in design and desirable thermal shutdown temperature. r k 125 p thdn temperature 253 83.3 k (2) figure 36 shows the relationship between r tmon and p- thdn temperature. increasing the r tmon value results in a lower p-thdn temperat ure. the system designer can define the shutdown te mperature of FDMF5820DC based on the system thermal design. the p-thdn is a latch-off shutdown, so the (por) on vcc is needs to re-enable t he gate driver. if not using tmon / p-thdn features, tie the tmon pin to agnd. figure 36. r tmon vs. p-thdn temperature catastrophic fault sps FDMF5820DC includes a catastrophic fault feature. if a hs mosfet shor t is detected, the driver internally pulls the en / fault# pin low and shuts down the sps driver. the intention is to implement a basic circuit to test the hs mosfet short by monitoring ldrv and the state of sw node. if a hs short fault is detected, the sps module clocks the fault latch shutting down the module. the module requires a vcc por event to restart. figure 37. catastrophic fault waveform
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 18 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor application information decoupling capacitor for pvcc & vcc for the supply inputs (pvcc and vcc pins), local decoupling capacitors are required to supply the peak driving current and to reduce noise during switching operation. use at least 0.68 ~ 1 f / 0402 ~ 0603 / x5r ~ x7r multi-layer ceramic capacitors for both power rails. keep these capacitors close to the pvcc and vcc pins and pgnd and agnd copper planes. if they need to be located on the bottom side of board, put through-hole vias on each pads of the decoupling capacitors to connect the capacitor pads on bottom with pvcc and vcc pins on top. the supply voltage range on pvcc and vcc is 4.5 v ~ 5.5 v, typically 5 v for normal applications. r-c filter on vcc the pvcc pin provides power to the gate drive of the high-side and low-side power mosfets. in most cases, pvcc can be connected directly to vcc, which is the pin that provides power to the analog and logic blocks of the driver. to avoid switching noise injection from pvcc into vcc, a filter resistor can be inserted between pvcc and vcc decoupling capacitors. recommended filter resistor value range is 0 ~ 10 ? , typically 0 ? for most applications. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ). a bootstrap capacitor of 0.1 ~ 0.22 f / 0402 ~ 0603 / x5r ~ x7r is usually appropriate for most switching applications. a se ries bootstrap resistor may be needed for specific applications to lower high-side mosfet switching speed. the boot resistor is required when the sps is switching above 15 v v in ; when it is effective at controlling v sw overshoot. r boot value from zero to 6 ? is typically recommended to reduce excessive voltage spike and ringing on the sw node. a higher r boot value can cause lower efficiency due to high switching loss of high-side mosfet. do not add a capacitor or resistor between the boot pin and gnd. en / fault# (input / output) the driver in sps is enabl ed by pulling the en pin high. the en pin has internal 250 k ? pull-down resistor, so it needs to be pulled-up to v cc with an external resistor or connected to the controller or system to follow up the command from them. if the en pin is floated, it cannot turn on the driver. the fault flag low signal is asserted on the en / fault# pin when the driv er temperature reaches p- thdn temperature or a high-side mosfet fault occurs. then the driver shuts down. the typical pull-up resistor value on en ~ vcc is 10 k ? . do not add a noise filter capacitor on the en pin. pwm (input) the pwm pin recognizes three different logic levels from pwm controller: high, low, and 3-state. when the pwm pin receives a high command, the gate driver turns on the high-side mosfet. when the pwm pin receives a low command, the gate driver turns on the low-side mosfet. when the pwm pin receives a voltage signal inside of the 3-state window (v tri_window ) and exceeds the 3-state hold-off time, the gate driver turns off both high-side and low-side mosfets. to recognize the high-impedance 3- state signal from the controller, the pwm pin has an internal resistor divider from vcc to pwm to agnd. the resistor divider sets a voltage level on the pwm pin inside the 3-state window when the pwm signal from the controller is high-impedance. zcd# (input) when the zcd# pin sets high, the zcd function is disabled and high-side and low-side mosfets switch in ccm (or fccm, forced ccm) by pwm signal. when the zcd# pin is low, the low-side mosfet turns off when the sps driver detects negative inductor current during the low-side mosfet turn-on period. this zcd feature allows higher conv erter efficiency under light- load condition and pfm / dcm operation. the zcd# pin has an internal current source from vcc, so it may not need an external pull-up resistor. once v cc is supplied and the driver is enabled, the zcd# pin holds logic high without external components and the driver operates switching in ccm or fccm. the zcd# pin can be grounded for autom atic diode emulation in dcm by the sps itself, or it can be connected to the controller or system to follow the command from them. the typical pull-up resistor value on zcd# ~ vcc is 10 k ? for stable zcd# high level. if not using the zcd feature, tie the zcd# pin to vcc with a pull-up resistor. do not add any noise filter capacitor on the zcd# pin. tmon (output) / p-thdn during normal operation (no fault detected), the tmon pin sources an analog current proportional to the absolute temperature of th e gate driver. with 25 k ? r tmon and 0.1 f c tmon on tmon pin to agnd, it outputs 1 v at 25c driver t j and 1.5 v at 150c driver t j . the c tmon is a filter capacitor to minimize switching noise injection onto the tmon pin. the tmon pin can be connected to a pwm contro ller or system controller and used to monitor the sps module temperature. if the tmon pin voltage exceeds 1.5 v with 25 k ? r tmon , the driver temperature is over 150c and the driver is shut down by the p-thdn feature. the 150c thermal shutdown temperature can be adjusted by the r tmon value to define the thdn temperature for the application. refer to the p-thdn section to define thermal shutdown temperature and r tmon value. if not using the tmon / p-thdn features, tie the tmon pin to gnd.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 19 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor power loss and efficiency figure 38 shows an example diagram for power loss and efficiency measurement. power loss calculation and equation examples: p in = (v in ? i in ) + (v cc ? i cc ) [w] p sw = v sw ? i out [w] p out = v out ? i out [w] p loss_module = p in ? p sw [w] p loss_total = p in ? p out [w] effi module = (p sw / p in ) ? 100 [%] effi total = (p out / p in ) ? 100 [%] figure 38. power loss and efficiency measurement diagram
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 20 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor pcb layout guideline figure 39 through figure 42 provide examples of single- phase and multi-phase layouts for the FDMF5820DC and critical components. all of the high-current paths; such as vin, sw, vout, and gnd coppers; should be short and wide for low parasitic inductance and resistance. this helps achieve a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. input ceramic bypass capacitors must be close to the vin and pgnd pins. this r educes the high-current power loop inductance and the input current ripple induced by the power mosfet switching operation. the sw copper trace serves two purposes. in addition to being the high-frequency current path from the sps package to the output inductor, it serves as a heat sink for the low-side mosfet. the trace should be short and wide enough to present a low-impedance path for the high-frequency, high-cur rent flow between the sps and the inductor. the short and wide trace minimizes electrical losses and sps temperature rise. the sw node is a high-voltage and high-frequency switching node with high noise potential. care should be taken to minimize coupling to adjacent traces. since this copper trace acts as a heat sink for the low-side mosfet, balance using the largest area possible to improve sps cooling while maintaining acceptable noise emission. an output inductor should be located close to the FDMF5820DC to minimize the power loss due to the sw copper trace. care should also be taken so the inductor dissipation does not heat the sps. powertrench ? mosfets are used in the output stage and are effective at minimizing ringing due to fast switching. in most cases, no rc snubber on sw node is required. if a snubber is used, it should be placed close to the sw and pgnd pins. the resistor and capacitor of the snubber must be sized properly to not generate excessive heating due to high power dissipation. decoupling capacitors on pvcc, vcc, and boot capacitors should be placed as close as possible to the pvcc ~ pgnd, vcc ~ agnd, and boot ~ phase pin pairs to ensure clean and stable power supply. their routing traces should be wide and short to minimize parasitic pcb resistance and inductance. the board layout should include a placeholder for small- value series boot resistor on boot ~ phase. the boot- loop size, including series r boot and c boot , should be as small as possible. a boot resistor may be required when the sps is operating above 15 v v in and it is effective to control the high-side mosfet turn-on slew rate and sw voltage overshoot. r boot can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative v sw ringing. inserting a boot resistance lowers the sps module efficiency. efficiency versus switching noise must be considered. r boot values from 0.5 ? to 6.0 ? are typically effective in reducing v sw overshoot. the vin and pgnd pins handle large current transients with frequency components greater than 100 mhz. if possible, these pins should be connected directly to the vin and board gnd planes. the use of thermal relief traces in series with these pins is not recommended since this adds extra parasit ic inductance to the power path. this added inductance in series with either the vin or pgnd pin degrades sy stem noise immunity by increasing positive and negative v sw ringing. pgnd pad and pins should be connected to the gnd copper plane with multiple vias for stable grounding. poor grounding can create a noisy and transient offset voltage level between pgnd and agnd. this could lead to faulty operation of gate driver and mosfets. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add any additional capacitors betw een boot to pgnd. this may lead to excess current flow through the boot diode, causing high power dissipation. the zcd# and en pins have weak internal pull-up and pull-down current sources, respectively. these pins should not have any noise filt er capacitors. do not float these pins unless absolutely necessary. put multiple vias on the vin and vout copper areas to interconnect top, inner, and bottom layers to evenly distribute current flow and heat conduction. do not put too many vias on the sw cop per to avoid extra parasitic inductance and noise on the switching waveform. as long as efficiency and thermal performance are acceptable, place only one sw node copper on the top layer and put no vias on the sw copper to minimize switch node parasitic noise. vias should be relatively large and of reasonably low inductance. critical high- frequency components; such as r boot , c boot , rc snubber, and bypass capacitors; should be located as close to the respective sps module pins as possible on the top layer of the pcb. if th is is not feasible, they can be placed on the board bottom side and their pins connected from bottom to top through a network of low- inductance vias.
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 21 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor pcb layout guideline (continued) figure 39. single-phase board layout example ? top view figure 40. single-phase board layout example ? bottom view (mirrored)
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 22 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor pcb layout guideline (continued) figure 41. 6-phase board layout example with 6 mm x 6 mm inductor ? top view figure 42. 6-phase board layout example with 6 mm x 6 mm inductor ? bottom view (mirrored)
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 23 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor physical dimension figure 43. 31-lead, clip bond pqfn sps, 5.0 mm x 5.0 mm package physical dimension package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/pq/pqfn31a.pdf . notes: unless otherwise specified a) does not fully conform to jedec registration mo-220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) drawing file name: mkt-pqfn31arev4 f) fairchildsemiconductor see detail 'a' detail 'a' scale: 2:1 seating plane top view front view c 0.30 0.20 0.05 0.00 0.80 0.70 0.10 c 0.08 c 5.000.10 5.000.10 0.10 c 2x b a 0.10 c 2x pin#1 indicator c.l. c.l. 1.63 3.53 (0.68) (0.82) (2x) (31x) 3.800.10 0.85 0.40 0.35 0.15 (0.85) 0.50 0.30 0.40 1.03 1.920.10 0.45 1.030.10 0.40 1.980.10 0.50 (0.38) 0.50 1.320.10 0.30 0.20 0.55 0.30 (0.22) 1.030.10 0.50 0.30 0.10 c a b 0.05 c pin #1 indicator bottom view c.l. c.l. 8 1 9 15 23 16 31 24 0.05 max 0.55 0.30 14 13 12 11 10 765432 30 29 28 27 26 25 17 18 19 20 21 22 32 33 8 9 1 15 24 16 23 31
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 24 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor land pattern recommendation figure 44. 31-lead, clip bond pqfn sps, 5.0 mm x 5.0 mm package land pattern recommendation package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/pq/pqfn31a.pdf .
? 2013 fairchild semiconductor corporation www.fairchildsemi.com FDMF5820DC ? rev. 1.0.1 25 FDMF5820DC ? smart power sta g e ( sps ) module with inte g rated tem p erature monitor

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